The present invention relates to a multi-layered wiring structure for use in electronic devices such as image sensors. More particularly, the present invention relates to a multi-layered wiring structure that reduces electrical effects between signal lines or thin-film transistors to insure that output electric charges will be correctly produced from signal lines or the source electrodes of thin-film transistors.
Common electronic devices having a multi-layered wiring structure are image sensors of facsimile equipment, scanners, etc. In conventional image sensors, particularly in contact image sensors, image information on a document or the like is projected in a one-to-one correspondence to pixels and converted to electric signals. In a certain type of image sensors, the projected image is divided into a multiple of pixels (light-receiving elements) and the charges generated in individual light-receiving elements are stored temporarily, for specified block units, in the capacitance between wires using thin-film transistor elements (TFT) and then read out sequentially as electric signals over time at a speed ranging from several hundred kilohertz to several megahertz. This type of image sensors, generally referred to as a "TFT-driven" image sensor, has the advantage that image can be read by a single driving IC on the basis of the action of TFTs and this contributes to the use of a smaller number of ICs for driving image sensors.
An equivalent circuit diagram for the TFT-driven image sensor is shown in FIG. 5. It basically consists of a linear array of light-receiving elements 11 that is generally equal in length to the width of a document, a charge transfer unit 12 composed of a plurality of thin-film transistors (Ti,j; i=1-N; j=1-n) that correspond to the individual light-receiving elements 11' in a one-to-one relationship, and matrix-shaped multi-layered wiring 13.
The array of light-receiving elements 11 is divided into N blocks of light-receiving elements and n light-receiving elements 11' in one block can be regarded to be equivalent to photodiodes (PDi,j; i=1-N; j=1-n). Each light-receiving element 11' is connected to the drain electrode of an associated thin-film transistor Ti,j. The source electrodes of thin-film transistors Ti,j are connected via the matrix-shaped multi-layered wiring 13 to n common signal lines 14 for each block of light-receiving elements, with the common signal lines 14 being further connected to a driving IC 15.
The gate electrodes of respective thin-film transistors Ti,j are connected to a gate pulse generator circuit (not shown) to establish conduction for each block. The photoelectric charges generated in respective light-receiving elements 11' are stored for a certain time in their parasitic capacitance and in the drain-gate over-lap capacitance of an associated thin-film transistor; thereafter, the charges are sequentially transferred, for each block, to the capacitance (Ci; i=1-n) between lines in multi-layered wiring 13 using the thin-film transistors Ti,j as switches for charge transfer and stored there for a certain period of time.
This process is described below in detail. In response to a gate pulse .phi.G1 from the gate pulse generator circuit, thin-film transistors T1,1-T1,n in the first block turn on and the charges stored temporarily after generation from the light-receiving elements 11' in the first block are transferred for storage in the associated mutual capacitance Ci. The stored charges cause changes in the potentials of the common signal lines 14 and the resulting voltage values are delivered to an output line 16 over time by sequentially turning on analog switches (SWi, i=1-n) in the driving IC 15.
Subsequently, in response to gate pulses .phi.G2-.phi.Gn, the thin-film transistors T2,1-T2,n up to TN,1-TN,n in the second to the Nth blocks are turned on, whereby the charges from the associated light-receiving elements are transferred for each block and read out sequentially so as to obtain a line of image signals from the documents in the fast scan direction. Then, the document is moved by a document feed means such as rollers (not shown) and the above procedure is repeated until image signals for the whole documents are obtained (see Japanese Patent Unexamined Publications No. Sho. 63-9358 and No. Sho. 63-67772).
A specific structure of the matrix-shaped multi-layered wiring 13 used in the prior art system described above is shown in cross section in FIG. 6. As shown, the wiring 13 comprises a substrate 21 having lower signal lines 31, an insulation layer 33 and upper signal lines 32 formed thereon in the order written. In the usual case, the lower signal lines 31 are arranged in such a way that they cross the upper signal lines 32 at right angles, with contact holes 34 being provided to establish connection between the upper and lower signal lines.
A problem with this configuration of the matrix-shaped multi-layered wiring 13 is that crosstalks can occur where the upper signal lines cross the lower signal lines (i.e., a phenomenon in which due to the capacitance that exists at the crossovers of signal lines, a change in the potential of one signal line will be transmitted via the capacitance to the other signal line, thereby changing the potential of the latter). To solve this problem, it has been proposed that an insulation layer 33a, a grounding sheet 35 connected to the ground and a insulation layer 33b are provided between the upper and lower signal lines as shown in cross section in FIG. 7, so that the occurrence of crosstalks is prevented by means of the grounding sheet 35 (see Japanese Patent Unexamined Publication No. Sho. 62-67864).
However, the use of a grounding sheet causes the following two major problems; first, substantial parasitic capacitance develops between each signal line and the grounding sheet; second, the grounding sheet can deflect to cause warpage in the image sensor itself. With a view to solving these problems, as shown in FIG. 8(a) (plan view) and FIG. 8(b) (cross-sectional view), it has been proposed to replace the grounding sheet with a grounding layer 36 that is made of mesh-shaped grounding member with centers at the crossovers of upper and lower signal lines (see Japanese Patent Unexamined Publication No. Sho. 64-5057). It should, however, be noted that for the sake of clarity, only one of each of upper and lower signal lines are shown in FIG. 8(a) by way of example.
Another prior art approach for preventing the occurrence of crosstalks between signal lines arranged parallel to one another in a common layer, is shown in FIG. 5 which is an equivalent circuit diagram for the conventional image sensor and shown more specifically in FIG. 9(a) which is a plan view and in FIG. 9(b) which is a cross section of FIG. 9(a) taken on the line C--C'. A shield line 37a connected to the ground is provided between two adjacent lower signal lines 31 formed in a common layer and another shield line 37b connected to the ground is also provided between two adjacent upper signal lines 32 formed in a common layer.
The major problem with the prior art configurations of the multi-layered wiring 13, particularly with the multi-layered wiring structure shown in FIGS. 9(a) and 9(b) is that as the pixels of an image sensor become finer or more closely packed to reduce its size, it becomes increasingly difficult and even impossible to provide a shield line 37 between adjacent signal lines in a common layer.
To state more specifically, the distance between signal lines that can be drawn from pixels is determined by the pitch of the latter. With current models of image sensors, each of the signal lines and shield lines has a line width of about 9 .mu.m and the distance between two adjacent signals or between a signal line and a shield line must be at least about 11 .mu.m. Thus, in order to provide a shield line having a width of about 9 .mu.m between two adjacent lines, a clearance of at least about 31 .mu.m (interline distance 11 .mu.m+shield line width 9 .mu.m+interline distance 11 .mu.m) is necessary. This condition can be met by a 400 SPI sensor since the pitch of pixels is as wide as about 63.5 .mu.m. However, if the pixels become finer and more closely packed to such an extent that their pitch is reduced to smaller than about 31 .mu.m, it is no longer possible to form a shield line between adjacent signal lines in a common layer in which those signal lines are formed. As a result, crosstalks occur between signal lines arranged parallel to one another in the common layer to make it impossible to read out electric charges in a correct way, and this eventually deteriorates the reproduction of gradation with the image sensor.
This problem does not solely occur between signal lines that are drawn from pixels. As for signal lines arranged parallel to the direction in which a plurality of elongated pixels are formed (i.e., the fast scan direction of the image sensor), namely, upper signal lines 32 shown in FIG. 9(a), the same problem occurs if the distance between adjacent signal lines decreases as in the case where the line width in the slow scan direction is reduced for constructing a compact image sensor.
The problem of crosstalks that occur between adjacent signal lines arranged parallel to each other in a common layer has also been found in the case where a plurality of thin-film transistors are arranged parallel to one another. Before going into details of this problems, let us describe the configuration of a thin-film transistor with reference to FIG. 10 which is a plan view and FIG. 11 which is a cross section of FIG. 10 taken on line D--D'.
The thin-film transistor has a reverse staggered structure and comprises a substrate 21 on which the following layers are superposed in the order written: a chromium (Cr 1) layer serving as a gate electrode 25; a silicon nitride film (SiNx 1) serving as a gate insulation layer 26; a hydrogenated amorphous silicon (a-Si:H) layer serving as a semiconductor active layer 27; a silicon nitride film (SiNx 2) serving as a channel protecting film 29 that is provided to face the gate electrode 25; an n.sup.+ hydrogenated amorphous silicon (n.sup.+ a-Si:H) layer serving as an ohmic contact layer 28; chromium (Cr 2) layers serving as a drain electrode 41 and a source electrode 42; a polyimide layer serving as an insulation layer; and an aluminum layer 30 that is formed on top of the polyimide layer in a position that is above the channel protecting layer 29 and which serves as a metal layer for isolating light to the a-Si:H layer 27.
In an actual device, a plurality of thin-film transistors having the above structure are arranged parallel to one another on the substrate 21 in such a way that the source electrode 42 of one thin-film transistor is positioned very close to the drain electrode 41 of an adjacent thin-film transistor. In each thin-film transistor, the drain electrode 41 usually experiences variations in potential in the order of several volts whereas the source electrode 42 experiences variations in potential in the order of several tens of millivolts. Hence, the source electrode 42 of one thin-film transistor is subject to variations in the potential of the drain electrode 41 of an adjacent thin-film transistor and the resulting crosstalk makes it impossible for electric charges to be correctly read out, whereby the reproduction of gradation from the image sensor is deteriorated.